Generally, best practice is to NOT instantiate a DSP block in Verilog or VHDL RTL code. The goal is to have the synthesis tool infer the DSP block during synthesis. This is an optimal use of resources, however the part has a finite number of DSP blocks which will limit the size of the transform.Īnother limitation is the bit width the Xilinx DSP48 block max size for multiply is 25x18. The 'pipeline' (registers) end up built into the DSP blocks, so they are somewhat free. In the code shown there are 4 multiplies and 4 adds, if this synthesizes as 4 DSP blocks this is the optimum result. The DSP blocks have a built in multiply and accumulate. In FPGA, when designing modules that multiply and add you want those resources to synthesize as DSP blocks. Can the below be considered as a safe/reliable design, if not can anyone who have experience building DSP modules suggest things to improve in my design. My question is : Can I keep all the multiplication and vector extraction all as combinational logic and only register the output at each stage, in order to pipeline the design. Wire p_real_w, p_imag_w, q_real_w, q_imag_w Īssign bw_real_real = b_real * w_real // acĪssign bw_imag_imag = b_imag * w_imag // bdĪssign bw_real_imag = b_real * w_imag // adĪssign bw_imag_real = b_imag * w_real // bcĪssign bw_real = bw_real_real - bw_imag_imag // ac - bdĪssign bw_imag = bw_real_imag + bw_imag_real // ad + bc Wire bw_real_real, bw_imag_imag, bw_real_imag, bw_imag_real // complex product outputs module simple_butterfly #(parameter WIDTH =16)( I need some input on having the minimal latency and at the same time have a stable design. I have build the simply butterfly module (see below). I am building a 4 stage FFT using a simple butterfly module to do the complex multiply and accumulate.
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